1. Field of the Invention
This invention relates in general to semiconductor devices and in particular to alignment aids for semiconductor devices.
2. Description of the Related Art
Alignment aids are utilized in the manufacture of semiconductor devices. With some processes, an alignment aid is scanned by a laser to provide an indication of location on a semiconductor wafer e.g. for the purpose of blowing fuses. Typically, an alignment aid includes an alignment feature area which provides a first level of reflectivity to light and a background area adjacent to the alignment feature that provides a second level of reflectivity to light that is in substantial contrast to the first level. With a positive density alignment aid, the alignment feature provides a high level of reflectivity to light and the background area provides a relatively low level of reflectivity to light.
With some alignment aids, the portion of the alignment aid providing the relatively low level of reflectivity to light (e.g. the background area for a positive density alignment aid) is void of metal in the metal interconnect layers of the background area. However, these alignment aids may experience problems due to uneven polishing of the interconnect layers from the lack of patterned metal in those areas. To overcome the above described uneven polishing problem, metal tiles may be located in each of the metal interconnect layers of the background areas for improved polishing of those areas.
However, the alignment aids described above are located over areas of the wafer that are void of active circuitry in the substrate or interconnect layers. Accordingly, alignment aids described above waste wafer space in that no active circuitry is located underneath the alignment aid.
What is needed is an alignment aid that can be located over active circuitry of a semiconductor device.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. FIGS. 1, 2, and 3 are not necessarily drawn to scale.